1. Technical Field
The present invention relates to field effect transistors (FETs), and more specifically, to asymmetric FETs.
2. Related Art
In a typical field effect transistor (FET), there is a trade-off between (a) the quality of the electric contacts coupled to the source/drain (S/D) regions of the FET (or in short, S/D contacts) and (b) the FET size. For example, to achieve better S/D contacts, the S/D regions can be doped more heavily. However, this increases the depth of dopants of the S/D regions and leads to degraded short-channel behaviors, such as increased Drain-Induced Barrier Lowering, increased subthreshold swing, and increased variability of threshold voltage. Thus it is noted that a channel being too short may have undesirable short channel effects. As a result, to keep the channel from being too short, the gate length must be increased so as to separate further the S/D regions from each other. This increases the size of the FET and costs more chip area, increases chip power, and increases circuit delay, which are undesirable.
Therefore, there is a need for an FET (and a method for forming the same) which has a better trade-off balance between the S/D contacts and FET size than that of the prior art.